1. Field of the Invention
The present invention relates to a semiconductor device including a nonvolatile memory unit in which data once stored therein can be rewritten and a variable logic unit whose logical functions can be set programmably, and relates to a technique for constructing such semiconductor device, the technique being effective in application to, for example, a microcomputer of a system-on-chip type or a system LSI.
2. Description of the Related Art
A technique for constructing arithmetic circuitry, using a variable logic unit which is called a Field Programmable Gate Array (EPGA) or a Field Programmable Logic Device (FPLD) is described in JP-A No. 111790/1998. A technique for constructing the EPGA, using electrically rewritable nonvolatile storage elements as its storage cells, the elements being used in an EEPROM and a flash memory, is described in xe2x80x9cInterfacexe2x80x9d pp. 67-68, published by CQ Publishing Co., Ltd. (November 2001).
A nonvolatile memory unit using split-gate-type nonvolatile memory cells is widely used for application in mounting with logical devices on a chip. This split-gate-type nonvolatile memory cell consists of two transistor portions: a memory MOS transistor portion for storing data and a selecting MOS transistor portion for selecting the memory transistor portion and retrieving the data therefrom. As publicly known literature in this relation, the technique hereof is described in the proceedings of the 1994 IEEE, VLSI Technology Symposium, pp. 71-72. The structure and operation of the split-gate-type nonvolatile memory cell will be briefly described. The split-gate-type nonvolatile memory cell is composed of a source, drain, floating gate, and control gate. The floating gate is formed in the memory MOS transistor portion and the gate electrode of the selecting MOS transistor portion makes the control gate. The gate oxide layer of the selecting MOS transistor portion is formed by deposition and functions as an electrically insulating layer between the floating gate and the gate electrode of the selecting MOS transistor. For example, to put the memory cell into the writing state, hot electrons are generated by source side injection and the floating gate is injected with charge. To put the memory cell into the erasure state, the charge retained on the floating gate is discharged from the tip of the floating gate toward the control gate. At this time, it is necessary to apply a high voltage of 12 volts to the control gate. The control gate that functions as a discharging electrode is, in essential, the gate electrode of the selecting MOS transistor portion that is used for selecting a read action.
The present inventors studied mounting a nonvolatile memory unit and a variable logic unit together with other components on a chip.
The purpose of mounting the variable logic unit together with a CPU and other components on a chip is to enable prompt reconfiguration to be performed adaptively to change in hardware specifications and functional change to the CPU and part of the peripheral functions. Moreover, the purpose of mounting the nonvolatile memory unit with the CPU on a chip is to store control program and data for the CPU operation into the on-chip memory so that debugging and program version up for CPU version up can be easily performed. The present inventors pursued the easiness of reconfiguring or upgrading the microcomputer and its peripheral functions by closely associating the variable logic unit with the nonvolatile memory unit. As a result, we discovered that it is important to accomplish quicker read access in both the nonvolatile memory unit and the variable logic unit and provide high reliability of functions to be realized by these units.
Once the variable logic unit is set to perform predetermined logic functions, the logic functions are performed through access to the nonvolatile memory unit and the CPU performs data processing through access to the nonvolatile memory unit. Thus, the nonvolatile memory unit that is applied in a mode that it is mounted with logic devices on a chip is especially required to have quicker read access performance. If the variable logic unit is configured with nonvolatile memory cells as its storage cells, the storage cells to function as switch elements are also required to have quicker read access performance.
In the above-mentioned split-gate-type memory cell structure, the gate electrode of the selecting MOS transistor functions as the electrode for erasure also. Thus, the gate insulation layer of the selecting MOS transistor had to have the same thickness as that of a high-voltage-tolerant MOS transistor for controlling the voltage for writing and erasure in order to assure its withstand voltage. Consequently, Gm (mutual conductance) of the selecting MOS transistor must be low, which makes it hard to obtain a sufficiently great current for reading. It was found that the above split-gate-type memory cell of prior art is not suitable for higher speed operation on a lower voltage with the view of quicker read access performance.
In view of functions to be realized by the nonvolatile memory unit and the variable logic unit, the variable logic unit determines a hardware configuration and the functions to be provided by the configuration are determined or adjusted by using the data stored in the nonvolatile memory unit. Thus, it was found that consideration should be taken to improve both the reliability of the data stored in the nonvolatile memory unit and the reliability of logic constitution definition data to be retained by the variable logic unit.
It is an object of the present invention is to configure a semiconductor device including a nonvolatile memory unit and a variable logic unit mounted on a chip to achieve higher speed operation on a lower voltage.
It is another object of the present invention is to configure a semiconductor device including a nonvolatile memory unit and a variable logic unit mounted on a chip to achieve high reliability of functions to be realized by these units.
It is a further object of the present invention is to provide a semiconductor device that enables reconfiguring or upgrading a CPU and other peripheral functions mounted thereon easily with a high reliability and can meet requirements of higher speed operation on a lower voltage.
The foregoing and other objects and new features of the invention will be apparent from the description herein and the accompanying drawing.
The advantages to be obtained by a typical semiconductor device provided by the present invention disclosed herein will be summarized below.
According to the invention, a nonvolatile memory cell that essentially has a split gate structure composed of a selecting MOS transistor (second MOS transistor) and a memory MOS transistor (first MOS transistor) is provided. The nonvolatile memory cell is constructed such that the dielectric withstand voltage of the gate of the selecting MOS transistor is lower than that of the memory MOS transistor or the physical or electrical thickness of the gate insulation layer of the selecting MOS transistor is thinner than that of a high-voltage-tolerant MOS transistor (fourth MOS transistor). This makes it possible that the selecting MOS transistor has a high Gm. Because of the high Gm, a sufficiently great current for reading can be obtained and quicker read access to the split-gate-type memory cell can be achieved. A semiconductor device of the invention including a nonvolatile memory unit and a variable logic unit can achieve higher speed operation on a lower voltage.
Current for writing is reduced. Moreover, by using MONOS-type nonvolatile memory cells, the semiconductor device of the invention including a nonvolatile memory unit and a variable logic unit can achieve high reliability of functions to be realized by the nonvolatile memory unit and the variable logic unit.
Furthermore, the semiconductor device of the invention enables reconfiguring or upgrading a CPU and other peripheral functions mounted thereon easily with a high reliability and can meet requirements of higher speed operation on a lower voltage.
The overview of a typical semiconductor device provided by the present invention disclosed herein will be summarized below.
[1] A semiconductor device according to the invention includes a nonvolatile memory unit which comprises a plurality of rewritable nonvolatile memory cells and a variable logic unit whose logical functions are determined in accordance with logic constitution definition data to be loaded into a plurality of storage cells thereof.
Each of the above-mentioned nonvolatile memory cells (NVC) comprises a first MOS transistor (Mtr) for storing data and a second MOS transistor (Str) for selecting the first MOS transistor. In a region of impurities under a section between a gate electrode of the first MOS transistor and a gate electrode of the second MOS transistor, no electrode common for both transistors is provided. These transistors are constructed such that the dielectric withstand voltage of the gate of the second MOS transistor is lower than that of the gate of the first MOS transistor. In another aspect, the thickness of the gate insulation layer of the second MOS transistor is noticed. When one of the above-mentioned nonvolatile memory cells is combined with a third MOS transistor (LMOS) which performs logic operation for memory action to the nonvolatile memory cell and a forth MOS transistor (HVMOS) which handles a voltage required for rewriting the data of the nonvolatile memory cell in the above-mentioned nonvolatile memory unit, gate insulation layers of the second, third, and fourth MOS transistors are formed to have their physical thicknesses fulfilling constraint tLxe2x89xa6ts less than tH where ts is the physical thickness of the gate insulation layer of the second MOS transistor, tL is the physical thickness of the gate insulation layer of the third MOS transistor, and tH is the physical thickness of the gate insulation layer of the fourth MOS transistor. The thickness may be regarded as electrical thickness instead of the physical thickness. Thinner electrical thickness means lower dielectric withstand voltage.
The above-mentioned nonvolatile memory cells have a split gate electrode structure that the gate electrode of the first MOS transistor to which a rather high voltage for writing and erasure is applied and the second selecting MOS transistor are separated and a common electrode is not provided in the region of impurities under the section between the separate gate electrodes. In virtue of this structure, a so-called source side injection and writing is accomplished by injection of hot electrons from the second MOS transistor side, the current for writing is reduced by restricting the channel current across the second MOS transistor, and the second MOS transistor can be made low voltage tolerant.
Moreover, the dielectric withstand voltage of the gate of the second selecting MOS transistor is set lower than that of the first MOS transistor which handles a voltage for writing and erasure. Alternatively, the physical or electrical thickness of the gate insulation layer of the second MOS transistor is made thinner than that of the fourth MOS transistor which handles a rather high voltage for rewriting data. This makes it possible that the second MOS transistor has a high Gm. The thickness of the gate insulation layer of the second MOS transistor, if it is made the possible thinnest, can be set equal to the thickness of the corresponding layer of the third MOS transistor that is responsible for logic operation. Because of the high Gm, a sufficiently great current for reading can be obtained and quicker access to the split-gate-type memory cells can be achieved. For reducing the current for writing and quicker read access, the semiconductor integrated circuitry having the nonvolatile memory cells is a promising solution to realizing operation on a lower voltage and quicker read access.
[2] As the storage cells of the above-mentioned variable logic unit, static lathes or nonvolatile memory cells may be used. If the latter is used, a storage cell also serves as a switch cell for selecting a logic constitution. Because the number of elements to constitute the storage is few, the area occupied by the variable logic unit on a chip can be reduced.
The nonvolatile memory cells having the same structure as those used in the above nonvolatile memory unit may be used in the variable logic unit. The variable logic unit using such nonvolatile memory cells is ideal for operation on a lower voltage and contributes to quicker logic operation.
[3] In a specific mode of the foregoing semiconductor device, the first transistor may use a conductive floating gate electrode (for example, a polysilicon gate electrode) covered with an insulation layer as a charge-storing region under its gate electrode. The charge-storing region may be provided by a charge-trapping insulation layer (a silicon nitride layer) covered with an insulation layer or a conductive particles layer covered with an insulation layer. If either of the latter two types of layers is used, its insulation property can effectively prevent leakage of charge stored and high reliability of retaining data can be achieved.
[4] In one preferred specific mode of the foregoing semiconductor device, the concentration of impurities existing in a channel region of the first MOS transistor is set lower than the concentration of impurities existing in a channel region of the second MOS transistor. The concentration of impurities in the channel that determines the threshold voltage of the second selecting MOS transistor, for example, the concentration of p-type impurities, is set thicker (higher) than that of the first MOS transistor so that the threshold voltage of the second MOS transistor will be positive. The concentration of impurities in the channel of the first MOS transistor for storing data, for example, the concentration of p-type impurities, is set lower than that of the second selecting MOS transistor so that the first MOS transistor""s threshold voltage during an erasure state will be sufficiently low and a great current for reading can be obtained. If a low supply voltage, for example, 1.8 V is used, the first MOS transistor""s threshold voltage during the erasure state can be set negative. When a relatively great variation (for example, 0.7 V) in the threshold voltage of a MOS transistor is considered, the gate electrode (memory gate electrode) of the first MOS transistor can be set at ground potential of the circuit during a read.
[5] The foregoing semiconductor device may be built on a single semiconductor chip. In the alternative, the foregoing semiconductor device may be configured such that the nonvolatile memory unit and the variable logic unit are separately built on different semiconductor chips and the semiconductor chips are mounted on a wiring substrate.
[6] An organic relationship between the nonvolatile memory unit and the variable logic unit is noticed. If the semiconductor device includes a CPU which is connected to the nonvolatile memory unit and the variable logic unit and the storage cells of the variable logic unit are the above-mentioned nonvolatile memory cells, programmed logic constitution definition data may be retained in the nonvolatile memory cells. Moreover, the nonvolatile memory unit may retain a control program for operation of the CPU which uses logical functions set, according to the logic constitution definition data retained in the variable logic unit. In other words, the semiconductor device includes a microcomputer portion which includes a plurality of rewritable nonvolatile memory cells in which a control program for microcomputer operation is stored and a variable logic unit which includes a plurality of rewritable storage cells in which logic constitution definition data is stored, wherein the microcomputer portion and the variable logic unit are programmable.
If the storage cells of the variable logic unit are the above-mentioned static latches, the nonvolatile memory unit may retain logic constitution definition data programmed for the variable logic unit in its nonvolatile memory cells. At the same time, it is preferable that the nonvolatile memory unit retains a transfer control program which is executed by the CPU to load the logic constitution definition data into storage cells of the variable logic unit. Furthermore, the nonvolatile memory unit may retain a control program for operation of the CPU which uses logical functions set, according to the logic constitution definition data loaded into said variable logic unit.
With the advantage that the current for reading is easy to obtain even with operation on a lower voltage, the semiconductor device of the invention can accomplish high reliability of functions to be realized by the nonvolatile memory unit and the variable logic unit mounted on a chip.